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25-bit address sequence specify which page of the main memory array to read, and the
last 11 bits (BA10 - BA0) of the 25-bit address sequence specify the starting byte
address within the page. The 24 or 19 don ’t care clock cycles that follow the four
address bytes are needed to initialize the read operation. Following the don’t care clock
cycles, additional clock pulses on the SCK/CLK pin will result in data being output on
either the SO (serial output) pin or the eight output pins (I/O7- I/O0).
The CS pin must remain low during the loading of the opcode, the address bytes, the
don’t care bytes, and the reading of data. When the end of a page in main memory is
reached during a Continuous Array Read, the device will continue reading at the begin-
ning of the next page with no delays incurred during the page boundary crossover (the
crossover from the end of one page to the beginning of the next page). When the last bit
(or byte if using the 8-bit interface mode) in the main memory array has been read, the
device will continue reading back at the beginning of the first page of memory. As with
crossing over page boundaries, no delays will be incurred when wrapping around from
the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the
output pins (SO or I/O7-I/O0). The maximum SCK/CLK frequency allowable for the Con-
tinuous Array Read is defined by the f CAR specification. The Continuous Array Read
bypasses both data buffers and leaves the contents of the buffers unchanged.
MAIN MEMORY PAGE READ: A main memory page read allows the user to read data
directly from any one of the 16384 pages in the main memory, bypassing both of the
data buffers and leaving the contents of the buffers unchanged. To start a page read, an
opcode of D2H must be clocked into the device followed by four address bytes (which
comprise 7 don’t care bits plus the 25-bit page and byte address sequence) and a series
of don’t care clock cycles (24 if using the serial interface or 19 if using the 8-bit inter-
face). The first 14 bits (PA13 - PA0) of the 25-bit address sequence specify the page in
main memory to be read, and the last 11 bits (BA10 - BA0) of the 25-bit address
sequence specify the starting byte address within that page. The 24 or 19 don’t care
clock cycles that follow the four address bytes are sent to initialize the read operation.
Following the don’t care bytes, additional pulses on SCK/CLK result in data being output
on either the SO (serial output) pin or the eight output pins (I/O7 - I/O0). The CS pin
must remain low during the loading of the opcode, the address bytes, the don’t care
bytes, and the reading of data. When the end of a page in main memory is reached, the
device will continue reading back at the beginning of the same page. A low-to-high tran-
sition on the CS pin will terminate the read operation and tri-state the output pins (SO or
I/O7 - I/O0). The maximum SCK/CLK frequency allowable for the Main Memory Page
Read is defined by the f SCK specification. The Main Memory Page Read bypasses both
data buffers and leaves the contents of the buffers unchanged.
BUFFER READ: Data can be read from either one of the two buffers, using different
opcodes to specify which buffer to read from. With the serial interface, an opcode of
D4H is used to read data from buffer 1, and an opcode of D6H is used to read data from
buffer 2. Likewise with the 8-bit interface an opcode of 54H is used to read data from
buffer 1 and an opcode of 56H is used to read data from buffer 2. To perform a buffer
read, the opcode must be clocked into the device followed by four address bytes com-
prised of 21 don’t care bits and 11 buffer address bits (BFA10 - BFA0). Following the
four address bytes, additional don’t care bytes (one byte if using the serial interface or
two bytes if using the 8-bit interface) must be clocked in to initialize the read operation.
Since the buffer size is 1056 bytes, 11 buffer address bits are required to specify the first
byte of data to be read from the buffer. The CS pin must remain low during the loading
of the opcode, the address bytes, the don’t care bytes, and the reading of data. When
the end of a buffer is reached, the device will continue reading back at the beginning of
the buffer. A low-to-high transition on the CS pin will terminate the read operation and
tri-state the output pins (SO or I/O7 - I/O0).
4
AT45CS1282 [Preliminary]
3447A–DFLSH–2/04
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